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TJA1080ATS/2
FlexRay transceiver
Rev. 04 -- 19 February 2009 Product data sheet
1. General description
The TJA1080ATS/2 is a FlexRay transceiver that is fully compliant with the FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1) and partly complies with version V2.1 Rev. B. It is primarily intended for communication systems from 1 Mbit/s to 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1080ATS/2 can be configured to be used as an active star transceiver or as a node transceiver. The TJA1080ATS/2 provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as high ESD protection. The TJA1080ATS/2 actively monitors the system performance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring. The TJA1080ATS/2 supports the mode control as used in NXP Semiconductors TJA1054 (see Ref. 2) and TJA1041 (see Ref. 3) CAN transceivers. The TJA1080ATS/2 is the next step up from the TJA1080 FlexRay transceiver (Ref. 4). Being fully pin compatible and offering the same excellent ESD protection, the TJA1080ATS/2 also features:
* * * *
Improved power-on reset concept Improved ElectroMagnetic Emission (EME) Support of 60 ns minimum bit time Improved bus error detection functionality
This makes the TJA1080ATS/2 an excellent choice in any kind of FlexRay node. See Section 14 for a detailed overview of differences between the TJA1080 and the TJA1080ATS/2.
2. Features
2.1 Optimized for time triggered communication systems
I I I I Compliant with FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1) Automotive product qualification in accordance with AEC-Q100 Data transfer up to 10 Mbit/s Support of 60 ns minimum bit time
NXP Semiconductors
TJA1080ATS/2
FlexRay transceiver
I Very low EME to support unshielded cable I Differential receiver with high common-mode range for ElectroMagnetic Immunity (EMI) I Auto I/O level adaptation to host controller supply voltage VIO I Usable for 14 V and 42 V powered systems I Bus guardian interface included I Independent power supply ramp-up for VBAT, VCC and VIO I Transceiver can be used for linear passive bus topologies as well as active star topologies
2.2 Low power management
I I I I I I Low power management including two inhibit switches Very low current in Sleep and Standby modes Local and remote wake-up Supports remote wake-up via dedicated data frames Wake-up source recognition Automatic power-down (in Star-sleep mode) in star configuration
2.3 Diagnosis (detection and signalling)
I I I I I I Overtemperature detection Short-circuit on bus lines VBAT power-on flag (first battery connection and cold start) Pin TXEN and pin BGE clamping Undervoltage detection on pins VBAT, VCC and VIO Wake source indication
2.4 Protections
I Bus pins protected against 8 kV HBM ESD pulses I Bus pins protected against transients in automotive environment (ISO 7637 class C compliant) I Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground I Fail-safe mode in case of an undervoltage on pins VBAT, VCC or VIO I Passive behavior of bus lines in the event that transceiver is not powered
2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1)
I I I I I I Bus driver voltage regulator control Bus driver - bus guardian control interface Bus driver logic level adaptation Active star - communication controller interface Active star - bus guardian interface Active star voltage regulator control
TJA1080A_4
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TJA1080ATS/2
FlexRay transceiver
3. Ordering information
Table 1. Ordering information Package Name TJA1080ATS/2 SSOP20 Description plastic shrink small outline package; 20 leads; body width 5.3 mm Version SOT339-1 Type number
TJA1080A_4
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Product data sheet
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TJA1080ATS/2
FlexRay transceiver
4. Block diagram
VIO 4 VCC 19 VBUF 20 VBAT 14 1 2
INH2 INH1
TJA1080ATS/2
11
TRXD0
18 SIGNAL ROUTER TRXD1 10 TRANSMITTER 17
BP BM
VIO
TXD TXEN BGE STBN EN
5 6 8 9 3 INPUT VOLTAGE ADAPTATION BUS FAILURE DETECTION
RXD ERRN RXEN
7 13 12 VBAT
OUTPUT VOLTAGE ADAPTATION
RXDINT STATE MACHINE RXDINT NORMAL RECEIVER
WAKE
15
WAKE-UP DETECTION
OVERTEMPERATURE DETECTION
OSCILLATOR LOWPOWER RECEIVER
UNDERVOLTAGE DETECTION
16
015aaa051
GND
Fig 1.
Block diagram
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TJA1080ATS/2
FlexRay transceiver
5. Pinning information
5.1 Pinning
INH2 INH1 EN VIO TXD TXEN RXD BGE STBN
1 2 3 4 5 6 7 8 9
20 VBUF 19 VCC 18 BP 17 BM 16 GND 15 WAKE 14 VBAT 13 ERRN 12 RXEN 11 TRXD0
015aaa052
TJA1080ATS/2
TRXD1 10
Fig 2.
Pin configuration
5.2 Pin description
Table 2. INH2 INH1 EN VIO TXD TXEN RXD BGE STBN TRXD1 TRXD0 RXEN ERRN VBAT WAKE GND BM BP VCC VBUF
TJA1080A_4
Pin description Type O O I P I I O I I I/O I/O O O P I P I/O I/O P P Description inhibit 2 output for switching external voltage regulator inhibit 1 output for switching external voltage regulator enable input; when HIGH enabled; internal pull-down supply voltage for VIO voltage level adaptation transmit data input; internal pull-down transmitter enable input; when HIGH transmitter disabled; internal pull-up receive data output bus guardian enable input; when LOW transmitter disabled; internal pull-down standby input; low-power mode when LOW; internal pull-down data bus line 1 for inner star connection data bus line 0 for inner star connection receive data enable output; when LOW bus activity detected error diagnoses output; when LOW error detected battery supply voltage local wake-up input; internal pull-up or pull-down (depends on voltage at pin WAKE) ground bus line minus bus line plus supply voltage (+5 V) buffer supply voltage
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Symbol Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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TJA1080ATS/2
FlexRay transceiver
6. Functional description
The block diagram of the total transceiver is illustrated in Figure 1.
6.1 Operating configurations
6.1.1 Node configuration
In node configuration the transceiver operates as a stand-alone transceiver. The transceiver can be configured as node by connecting pins TRXD0 and TRXD1 to ground during a power-on situation (PWON flag is set). The configuration will be latched when the PWON flag is reset, see Section 6.7.4. The following operating modes are available:
* * * * *
Normal (normal power mode) Receive-only (normal power mode) Standby (low power mode) Go-to-sleep (low power mode) Sleep (low power mode)
6.1.2 Star configuration
In star configuration the transceiver operates as a branch of a FlexRay active star. The transceiver can be configured as star by connecting pin TRXD0 or TRXD1 to VBUF during a PWON situation (PWON flag is set). The configuration will be latched when the PWON flag is reset, see Section 6.7.4 "Power-on flag". It is possible to redirect data from one branch to other branches via the inner bus. It is also possible to send data to all branches via pin TXD, if pins TXEN and BGE have the correct polarity. The following operating modes are available:
* * * * * *
Star-idle (normal power mode) Star-transmit (normal power mode) Star-receive (normal power mode) Star-sleep (low power mode) Star-standby (low power mode) Star-locked (normal power mode)
In the star configuration all modes are autonomously controlled by the transceiver, except in the case of a wake-up.
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Product data sheet
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TJA1080ATS/2
FlexRay transceiver
6.1.3 Bus activity and idle detection
The following mechanisms for activity and idle detection are valid for node and star configurations in normal power modes:
* If the absolute differential voltage on the bus lines is higher than |Vi(dif)det(act)| for
tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to LOW which results in pin RXD being released: - If, after bus activity detection, the differential voltage on the bus lines is higher than VIH(dif), pin RXD will go HIGH - If, after bus activity detection, the differential voltage on the bus lines is lower than VIL(dif), pin RXD will go LOW
* If the absolute differential voltage on the bus lines is lower than |Vi(dif)det(act)| for
tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH. This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH) Additionally, in star configuration, activity and idle can be detected (see Figure 6 for state transitions due to activity/idle detection in star configuration):
* If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN * If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN * If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on
pins TRXD0 and TRXD1
* If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on
pins TRXD0 and TRXD1
6.2 Operating modes in node configuration
The TJA1080ATS/2 provides two control pins STBN and EN in order to select one of the modes of operation in node configuration. See Table 3 for a detailed description of the pin signalling in node configuration, and Figure 3 for the timing diagram. All modes are directly controlled via pins EN and STBN unless an undervoltage situation is present. If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates the status of the error flag.
Table 3. Mode Normal Receive-only Go-to-sleep Standby Sleep
[1] [2] [3]
Pin signalling in node configuration STBN EN HIGH HIGH LOW LOW LOW ERRN[1] LOW HIGH RXEN LOW bus activity HIGH bus idle RXD LOW bus DATA_0 wake flag set[2] HIGH bus enabled DATA_1 disabled or idle wake flag reset HIGH HIGH Transmitter INH1 INH2
HIGH error flag error flag reset LOW set HIGH error flag error flag [2] reset LOW set X
wake flag wake set[2] flag reset
float[3] float float
Pin ERRN provides a serial interface for retrieving diagnostic information. Valid if VIO and (VBUF or VBAT) are present. If wake flag is not set.
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TJA1080A_4
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NXP Semiconductors
TJA1080ATS/2
FlexRay transceiver
TXD
BGE
TXEN
BP BM
RXEN
RXD
001aae439
Fig 3.
Timing diagram in Normal mode node configuration
normal
receive only
standby
receive only
normal
STBN tdet(EN)
0.7VIO 0.3VIO td(STBN-INH2) td(STBN-RXD) 0.7VIO 0.3VIO tdet(EN)
EN
ERRN
S2
001aag894
Fig 4.
Timing diagram of control pins EN and STBN
The state diagram in node configuration is illustrated in Figure 5.
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TJA1080ATS/2
FlexRay transceiver
1 RECEIVE ONLY STBN = HIGH EN = LOW 4 NORMAL STBN = HIGH EN = HIGH
3, 30 15, 25, 42, 43 31, 32 8, 17, 39 6, 33 11, 21
5 10, 20 7, 16, 38 2 14, 24, 40, 41 28, 29
12, 22 STANDBY(1) 19 STBN = LOW EN = LOW 9, 18 GO-TO-SLEEP STBN = LOW EN = HIGH 23
36, 37 26, 44
13, 34, 35 27, 45
SLEEP STBN = LOW EN = X
001aae438
(1) At the first battery connection the transceiver will enter the Standby mode.
Fig 5.
State diagram in node configuration
The state transitions are represented with numbers, which correspond with the numbers in column 3 of Table 4 to Table 7.
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Product data sheet Rev. 04 -- 19 February 2009
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NXP Semiconductors
Table 4. State transitions forced by EN and STBN (node configuration) indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Normal Direction to mode Transition number Pin STBN H L L H L L H H L H H L L H H EN L H L H H L H L H H L L H H L Flag UVVIO cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared 2 cleared 2 cleared UVVBAT cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared 2 cleared 2 cleared UVVCC cleared cleared cleared cleared cleared cleared 2 cleared 2 cleared X cleared cleared X X 2 cleared 2 cleared PWON cleared cleared cleared X X X X X X X X X X X X Wake cleared cleared cleared X X X 1 cleared 1 set X 1 cleared 1 set X cleared 1 cleared 1 set
[2][4] [2][4] [4] [5] [2][3] [2][3] [2][3] [2][3] [1]
Note
Receive-only 1 Go-to-sleep Standby 2 3 4 5 6 7 9 10 12 13 14
Receive-only Normal Go-to-sleep Standby Standby Normal Go-to-sleep Go-to-sleep Normal Standby Sleep Sleep Normal
Receive-only 8
Receive-only 11
Receive-only 15
[1] [2] [3] [4] [5]
STBN must be set to LOW at least tdet(EN) after the falling edge on EN. Positive edge on pin STBN sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. Hold time of go-to-sleep is less than th(gotosleep). Hold time of go-to-sleep becomes greater than th(gotosleep).
TJA1080ATS/2
FlexRay transceiver
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Product data sheet Rev. 04 -- 19 February 2009
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NXP Semiconductors
Table 5. State transitions forced by a wake-up (node configuration) indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Standby Direction to mode Normal Receive-only Go-to-sleep Standby Go-to-sleep Normal Receive-only Standby Go-to-sleep Sleep Normal Receive-only Standby Go-to-sleep
[1] [2]
Transition number 16 17 18 19 20 21 22 23 24 25 26 27
Pin STBN H H L L H H L L H H L L EN H L H L H L L H H L L H
Flag UVVIO cleared cleared cleared cleared cleared cleared cleared cleared 1 cleared 1 cleared 1 cleared 1 cleared UVVBAT cleared cleared cleared cleared cleared cleared cleared cleared 1 cleared 1 cleared 1 cleared 1 cleared UVVCC 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared PWON X X X X X X X X X X X X Wake set set set set set set set set set set set set
Note
[1] [1] [1] [1] [1] [1] [1] [1] [1][2] [1][2] [1] [1][2]
Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flag. Transition via Standby mode.
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FlexRay transceiver
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Product data sheet Rev. 04 -- 19 February 2009
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NXP Semiconductors
Table 6. State transitions forced by an undervoltage condition (node configuration) indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Normal Direction to mode Sleep Sleep Standby Receive-only Sleep Sleep Standby Go-to-sleep Standby Sleep Sleep Sleep Sleep
[1] [2] [3]
Transition number 28 29 30 31 32 33 34 35 36 37
Flag UVVIO set cleared cleared set cleared cleared set cleared set cleared UVVBAT cleared set cleared cleared set cleared cleared set cleared set UVVCC cleared cleared set cleared cleared set cleared cleared X X PWON cleared cleared cleared X X X X X X X Wake cleared cleared cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared
Note
[1] [1] [1] [1] [1] [1] [1] [1] [1][2] [1][3]
UVVIO, UVVBAT or UVVCC detected clears the wake flag. UVVIO overrules UVVCC. UVVBAT overrules UVVCC.
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FlexRay transceiver
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Product data sheet Rev. 04 -- 19 February 2009
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NXP Semiconductors
Table 7. State transitions forced by an undervoltage recovery (node configuration) indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Standby Sleep Direction to mode Normal Normal Normal Transition number 38 40 41 Pin STBN H H H H H H L L L L EN H L H H L L L X H X Flag UVVIO cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared UVVBAT cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared UVVCC cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared PWON X X X X X X X X X X Wake X X 1 cleared X 1 set X 1 set cleared 1 set cleared
[1] [1] [2][3] [4] [2][3] [4] [2][3] [4] [2][3] [4]
Note
Receive-only 39
Receive-only 42 Receive-only 43 Standby Sleep Go-to-sleep Sleep
[1] [2] [3] [4] Recovery of UVVCC flag. Recovery of UVVBAT flag.
44 45 46 47
Clearing the UVVBAT flag sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. Recovery of UVVIO flag.
TJA1080ATS/2
FlexRay transceiver
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FlexRay transceiver
6.2.1 Normal mode
In Normal mode the transceiver is able to transmit and receive data via the bus lines BP and BM. The output of the normal receiver is directly connected to pin RXD. The transmitter behavior in Normal mode of operation, with no time-out present on pins TXEN and BGE and the temperature flag not set, is given in Table 8. In this mode pins INH1 and INH2 are set HIGH.
Table 8. BGE L X H H X H L L Transmitter function table TXEN TXD X X H L Transmitter transmitter is disabled transmitter is disabled transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH
6.2.2 Receive-only mode
In Receive-only mode the transceiver can only receive data. The transmitter is disabled, regardless of the voltages on pins BGE and TXEN. In this mode pins INH1 and INH2 are set HIGH.
6.2.3 Standby mode
In Standby mode the transceiver has entered a low power mode which means very low current consumption. In the Standby mode the device is not able to transmit or receive data and the low power receiver is activated to monitor for bus wake-up patterns. Standby mode can be entered if the correct polarity is applied to pins EN and STBN (see Figure 5 and Table 4) or an undervoltage is present on pin VCC; see Figure 5. In this mode, pin INH1 is set HIGH. If the wake flag is set, pin INH2 is set to HIGH and pins RXEN and RXD are set to LOW, otherwise pin INH2 is floating and pins RXEN and RXD are set to HIGH; see Section 6.5.
6.2.4 Go-to-sleep mode
In this mode the transceiver behaves as in Standby mode. If this mode is selected for a longer time than the go-to-sleep hold time parameter (minimum hold time) and the wake flag has been previously cleared, the transceiver will enter Sleep mode, regardless of the voltage on pin EN.
TJA1080A_4
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TJA1080ATS/2
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6.2.5 Sleep mode
In Sleep mode the transceiver has entered a low power mode. The only difference with Standby mode is that pin INH1 is also set floating. Sleep mode is also entered if the UVVIO or UVVBAT flag is set. In case of an undervoltage on pin VCC or VBAT while VIO is present, the wake flag is set by a positive edge on pin STBN. The undervoltage flags will be reset by setting the wake flag, and therefore the transceiver will enter the mode indicated on pins EN and STBN if VIO is present. A detailed description of the wake-up mechanism is given in Section 6.5.
6.3 Operating modes in star configuration
In star configuration mode control via pins EN and STBN is not possible. The transceiver autonomously controls the operating modes except in the case of wake-up. The timing diagram of a transceiver configured in star configuration is illustrated in Figure 7. The state diagram in star configuration is illustrated in Figure 6. A detailed description of the pin signalling in star configuration is given in Table 9. If VIO and (VBUF or VBAT) are within their operating range, pin ERRN will indicate the error flag.
Table 9. Mode Star-transmit Star-receive Star-idle Star-locked Star-standby Star-sleep
[1] [2] [3] [4]
Pin signalling in star configuration TRXD0 / TRXD1 output[2] input[3] output input input input input error flag error flag wake flag wake flag wake flag wake flag reset set[4] reset set[4] reset set[4] float float ERRN[1] LOW HIGH RXEN LOW HIGH bus idle RXD LOW bus DATA_0 HIGH bus DATA_1 or idle enabled disabled HIGH HIGH Transmitter INH1 INH2
error flag error flag bus set reset activity
Pin ERRN provides a serial interface for retrieving diagnostic information. TRXD lines switched as output if TXEN activity is the initiator for Star-transmit mode. TRXD lines are switched as input if TRXD activity is the initiator for Star-transmit mode. Valid if VIO and (VBUF or VBAT) are present.
Pin BGE must be HIGH in order to enable the transmitter via pin TXEN. If pin BGE is LOW, it is not possible to activate the transmitter via pin TXEN. If pin TXEN is not used (no controller connected to the transceiver), it has to be connected to pin GND in order to prevent TXEN activity detection. In all normal modes pin RXD is connected to the output of the normal mode receiver and therefore represents the data on the bus lines.
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FlexRay transceiver
STAR LOCKED INH1 = HIGH INH2 = HIGH TXEN activity detected for longer than tto(tx-locked) idle detected on the bus lines and TXEN for longer than tto(locked-idle) bus activity detected for longer than tto(rx-locked)
STAR TRANSMIT INH1 = HIGH INH2 = HIGH
idle detected on TRXD0, TRXD1, TXEN and the bus lines
STAR IDLE INH1 = HIGH INH2 = HIGH
idle detected on TRXD0, TRXD1, TXEN and the bus lines
STAR RECEIVE INH1 = HIGH INH2 = HIGH
TRXD0, TRXD1, TXEN activity detected
bus activity detected wake flag 1 or UVVCC signal 0
wake flag 1 time in star locked longer than tto(locked-sleep) no acivity on TRXD0, TRXD1, TXEN and the bus lines for longer than tto(idle-sleep)
STAR SLEEP INH1 = floating INH2 = floating
STAR STANDBY(1) INH1 = HIGH INH2 = HIGH from star idle, star transmit or star receive if wake flag set and under voltage present on VCC for longer than t > tto(uv)(VCC)
from any mode if UVVCC flag is set regardless PWON flag
001aae441
(1) At the first battery connection the transceiver will enter the Star-standby mode.
Fig 6.
State diagram in star configuration
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FlexRay transceiver
star transmit TRXD0 TRXD1
star idle
star receive
star idle
star transmit
star idle
TXEN
TXD
TRXDOUT
BP BM
RXEN
RXD
001aae440
TRXDOUT is a virtual signal that indicates the state of the TRXD lines. TRXDOUT HIGH means TRXD lines switched as output. TRXDOUT LOW means TRXD lines switched as input.
Fig 7.
Timing diagram in star configuration
6.3.1 Star-idle mode
This mode is entered if one of the following events occurs:
* From Star-receive mode and Star-transmit mode if idle is detected on the bus lines, on
pin TXEN and on pins TRXD0 and TRXD1.
* If the transceiver is in Star-locked mode and idle is detected on the bus lines and pin
TXEN for longer than tto(locked-idle).
* If the transceiver is in Star-standby mode and the wake flag is set or no undervoltage
is present.
* If the transceiver is in Star-sleep mode and the wake flag is set, the transceiver enters
Star-idle mode in order to obtain a stable starting point (no glitches on the bus lines etc.). In Star-idle mode the transceiver monitors pins TXEN, TRXD0 and TRXD1 and the bus lines for activity. In this mode the transmitter is disabled.
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6.3.2 Star-transmit mode
This mode is entered if one of the following events occur:
* If the transceiver is in Star-idle mode and activity is detected on pin TXEN. * If the transceiver is in Star-idle mode and activity is detected on pins TRXD0 and
TRXD1. In Star-transmit mode the transmitter is enabled and the transceiver can transmit data on the bus lines and on the TRXD lines. It transmits the data received on pins TXD or TRXD0 and TRXD1, depending on where activity is detected:
* If activity is detected on the TRXD lines, the transceiver transmits data from pins
TRXD0 and TRXD1 to the bus.
* If activity is detected on the TXEN, the transceiver transmits data from pin TXD to the
bus and to the TRXD lines.
6.3.3 Star-receive mode
This mode is entered if the transceiver is in Star-idle mode and activity has been detected on the bus lines. In Star-receive mode the transceiver transmits data received on the bus via the TRXD0 and TRXD1 lines to other transceivers connected to the TRXD lines. The transmitter is always disabled. RXD, which represents the data on the bus lines, is output at TRXD0 and TRXD1.
6.3.4 Star-standby mode
This mode is entered if one of the following events occur:
* From Star-idle, Star-transmit or Star-receive modes if the wake flag is set and an
undervoltage on pin VCC is present for longer than tto(uv)(VCC).
* If the PWON flag is set.
In Star-standby mode the transceiver has entered a low power mode. In this mode the current consumption is as low as possible to prevent discharging the capacitor at pin VBUF. If pins VIO and VBUF are within their operating range, pins RXD and RXEN will indicate the wake flag.
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6.3.5 Star-sleep mode
This mode is entered if one of the following events occur:
* From any mode if an undervoltage on pin VCC is present for longer than tdet(uv)(VCC). * If the transceiver is in Star-idle mode and no activity is detected on the bus lines and
pins TXEN, TRXD0 and TRXD1 for longer than tto(idle-sleep).
* If Star-locked mode is active for longer than tto(locked-sleep).
In Star-sleep mode the transceiver has entered a low power mode. In this mode the current consumption is as low as possible to prevent the car battery from discharging. The inhibit switches are switched off. In this mode the wake flag wakes the transceiver. A detailed description of the wake-up mechanism is given in Section 6.5. If pins VIO and VBUF are within their operating range, pins RXD and RXEN will indicate the wake flag.
6.3.6 Star-locked mode
This mode is entered if one of the following events occur:
* If the transceiver is in Star-transmit mode and activity on pin TXEN is detected for
longer than tto(tx-locked).
* If the transceiver is in Star-receive mode and activity is detected on the bus lines for
longer than tto(rx-locked). This mode is a fail-silent mode and in this mode the transmitter is disabled.
6.4 Start-up
The TJA1080ATS/2 initialization is independent of the way the voltage supplies VBAT, VCC and VIO ramp up. A dedicated power-up sequence is not necessary.
6.4.1 Node configuration
Node configuration can be selected by applying a voltage lower than 0.3VBUF to pins TRXD0 and TRXD1 during power-on. Node configuration is latched by resetting the PWON flag while the voltage on pins TRXD0 and TRXD1 is lower than 0.3VBUF; see Section 6.7.4 for (re)setting the PWON flag.
6.4.2 Star configuration
Star configuration can be selected by applying a voltage higher than 0.7VBUF to pins TRXD0 or TRXD1 during power-on. Star configuration is latched by resetting the PWON flag while one of the voltages on pins TRXD0 or TRXD1 is higher than 0.7VBUF. See Section 6.7.4 for (re)setting the PWON flag. In this case the transceiver goes from Star-standby mode to Star-idle mode.
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6.5 Wake-up mechanism
6.5.1 Node configuration
In Sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Standby mode or Go-to-sleep mode (depending on the value at pin EN), if the wake flag is set. Consequently, pins INH1 and INH2 are switched on. If no undervoltage is present on pins VIO and VBAT, the transceiver switches immediately to the mode indicated on pins EN and STBN. In Standby, Go-to-sleep and Sleep modes pins RXD and RXEN are driven LOW if the wake flag is set.
6.5.2 Star configuration
In Star-sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Star-idle mode (pins INH1 and INH2 are switched on) if the wake flag is set. After entering Star-idle mode the transceiver monitors for activity to choose the appropriate mode transition (see Figure 6).
6.5.3 Remote wake-up
6.5.3.1 Bus wake-up via wake-up pattern Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated by an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least tdet(wake)idle are present on the bus lines within tdet(wake)tot.
tdet(wake)tot
0V Vdif -425 mV tdet(wake)Data_0 tdet(wake)idle tdet(wake)Data_0 tdet(wake)idle
001aae442
Fig 8.
Bus wake-up timing
6.5.3.2
Bus wake-up via dedicated FlexRay data frame The reception of a dedicated data frame, emulating a valid wake-up pattern, as shown in Figure 9, sets the wake-up flag of the TJA1080ATS/2. Due to the Byte Start Sequence (BSS), preceding each byte, the DATA_0 and DATA_1 phases for the wake-up symbol are interrupted every 1 s. For 10 Mbit/s the maximum interruption time is 130 ns. Such interruptions do not prevent the transceiver from recognizing the wake-up pattern in the payload of a data frame. The wake-up flag will not be set upon reception of an invalid wake-up pattern.
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Vdif 130 ns +1500 0V -1500 770 870 870 ns ns ns 5 s 130 130 ns ns 5 s 5 s 5 s
015aaa043
870 ns 870 ns
wake-up
Each interruption is 130 ns. The transition time from Data_0 to Data_1 and from Data_1 to Data_0 is about 20 ns. The TJA1080ATS/2 wake-up flag will be set with the following pattern: FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, FFh
Fig 9.
Minimum bus pattern for bus wake-up
6.5.4 Local wake-up via pin WAKE
If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than twake(WAKE) (falling edge on pin WAKE) a local wake-up event on pin WAKE is detected. At the same time, the biasing of this pin is switched to pull-down. If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than twake(WAKE), the biasing of this pin is switched to pull-up, and no local wake-up will be detected.
pull-up twake(WAKE) VBAT WAKE 0V
pull-down twake(WAKE)
pull-up
RXD and RXEN
INH1 and INH2
VBAT 0V
001aae443
Sleep mode: VIO and (VBAT or VCC) still provided.
Fig 10. Local wake-up timing via pin WAKE
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6.6 Fail silent behavior
In order to be fail silent, undervoltage detection and a reset mechanism for the digital state machine is implemented. If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver will enter a low power mode. This ensures a passive and defined behavior of the transmitter and receiver in case of an undervoltage detection. In the region between the minimum operating voltage and the undervoltage detection threshold, the principle function of the transmitter and receiver is maintained. However, in this region parameters (e.g. thresholds and delays of the transmitter and receiver) may deviate from the range specified for the operating range. The digital state machine is supplied by VCC, VIO or VBAT, depending on which voltage is available. Therefore, the digital state machine will be properly supplied as long as the voltage on pin VCC or pin VIO remains above 4.75 V or the voltage on pin VBAT remains above 6.5 V. If the voltage on all pins VCC, VIO and VBAT breaks down, a reset signal will be given to the digital state machine as soon as the internal supply voltage for the digital state machine is not sufficient for proper operation of the state machine. This ensures a passive and defined behavior of the digital state machine in case of an overall supply voltage breakdown.
6.6.1 VBAT undervoltage
* Node configuration: If the UVVBAT flag is set the transceiver will enter Sleep mode
(pins INH1 and INH2 are switched off) regardless of the voltage present on pins EN and STBN. If the undervoltage recovers the wake flag will be set and the transceiver will enter the mode determined by the voltages on pins EN and STBN.
* Star configuration: The TJA1080ATS/2 in star configuration is able to transmit and
receive data as long as VCC and VIO are within their operating ranges, regardless of the undervoltage on VBAT.
6.6.2 VCC undervoltage
* Node configuration: If the UVVCC flag is set the transceiver will enter the Standby
mode (pin INH2 is switched off) regardless of the voltage present on pins EN and STBN. If the undervoltage recovers or the wake flag is set mode switching via pins EN and STBN is possible.
* Star configuration: If the UVVCC flag is set the transceiver will enter the Star-sleep
mode.
6.6.3 VIO undervoltage
* Node configuration: If the voltage on pin VIO is lower than Vuvd(VIO) (even if the UVVIO
flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set the transceiver will enter Sleep mode (pins INH1 and INH2 are switched off). If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is possible.
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* Star configuration: If an undervoltage is present on pin VIO (even if the UVVIO flag is
reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set, pin INH1 is switched off. If an undervoltage is present on pin VIO and VCC is within the operating range, the TJA1080ATS/2 will forward the received data on TRXD or bus lines to all other branches.
6.7 Flags
6.7.1 Local wake-up source flag
The local wake-up source flag can only be set in a low power mode. When a wake-up event on pin WAKE is detected (see Section 6.5.4) it sets the local wake-up source flag. The local wake-up source flag is reset by entering a low power mode.
6.7.2 Remote wake-up source flag
The remote wake-up source flag can only be set in a low power mode if pin VBAT is within its operating range. When a remote wake-up event is detected on the bus lines (see Section 6.5.3) it sets the remote wake-up source flag. The remote wake-up source flag is reset by entering a low power mode.
6.7.3 Wake flag
The wake flag is set if one of the following events occurs:
* * * *
The local or remote wake-up source flag is set (edge sensitive) A positive edge is detected on pin STBN if VIO is present Recovery of the UVVBAT flag (only in node configuration) By recognizing activity on pins TRXD0 and TRXD1 (only in star configuration)
In node configuration the wake flag is reset by entering Normal mode, a low power mode or setting one of the undervoltage flags. In star configuration the wake flag is reset by entering a low power mode or by recovery of the UVVCC signal (without trec(uv)(VCC)).
6.7.4 Power-on flag
The PWON flag is set if the internal supply voltage for the digital part becomes higher than the lowest value it needs to operate. In node configuration, entering Normal mode resets the PWON flag. In star configuration the PWON flag is reset when the UVVCC signal goes LOW (no undervoltage detected).
6.7.5 Node configuration flag
Configuration flag set means node configuration.
6.7.6 Temperature medium flag
The temperature medium flag is set if the junction temperature exceeds Tj(warn)(medium) in a normal power mode while pin VBAT is within its operating range. The temperature medium flag is reset when the junction temperature drops below Tj(warn)(medium) in a normal power mode with pin VBAT within its operating range or after a read of the status register in a low power mode while pin VBAT is within its operating range. No action will be taken if this flag is set.
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6.7.7 Temperature high flag
The temperature high flag is set if the junction temperature exceeds Tj(dis)(high) in a normal power mode while pin VBAT is within its operating range. In node configuration the temperature high flag is reset if a negative edge is applied to pin TXEN while the junction temperature is lower than Tj(dis)(high) in a normal power mode with pin VBAT within its operating range. In star configuration, the temperature high flag is reset by any activity detection (edge) while the junction temperature is lower than Tj(dis)(high) in a normal power mode while pin VBAT is within its operating range. If the temperature high flag is set the transmitter is disabled and pins TRXD0 and TRXD1 are switched off.
6.7.8 TXEN_BGE clamped flag
The TXEN_BGE clamped flag is set if pin TXEN is LOW and pin BGE is HIGH for longer than tdetCL(TXEN_BGE). The TXEN_BGE clamped flag is reset if pin TXEN is HIGH or pin BGE is LOW. If the TXEN_BGE flag is set, the transmitter is disabled.
6.7.9 Bus error flag
The bus error flag is set if pin TXEN is LOW and pin BGE is HIGH and the data received from the bus lines (pins BP and BM) is different to that received on pin TXD. Additionally in star configuration the bus error flag is also set if the data received on the bus lines is different to that received on pins TRXD0 and TRXD1. The transmission of any valid communication element, including a wake-up pattern, does not lead to bus error indication. The error flag is reset if the data on the bus lines (pins BP and BM) is the same as on pin TXD or if the transmitter is disabled. No action will be taken if the bus error flag is set.
6.7.10 UVVBAT flag
The UVVBAT flag is set if the voltage on pin VBAT is lower than Vuvd(VBAT). The UVVBAT flag is reset if the voltage is higher than Vuvd(VBAT) or by setting the wake flag; see Section 6.6.1.
6.7.11 UVVCC flag
The UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than tdet(uv)(VCC). The flag is reset if the voltage on pin VCC is higher than Vuvd(VCC) for longer than trec(uv)(VCC) or the wake flag is set; see Section 6.6.2.
6.7.12 UVVIO flag
The UVVIO flag is set if the voltage on pin VIO is lower than Vuvd(VIO) for longer than tdet(uv)(VIO). The flag is reset if the voltage on pin VIO is higher than Vuvd(VIO) or the wake flag is set; see Section 6.6.3.
6.7.13 Error flag
The error flag is set if one of the status bits S4 to S12 is set. The error flag is reset if none of the S4 to S12 status bits are set; see Table 10.
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6.8 TRXD collision
A TRXD collision is detected when both TRXD lines are LOW for more than the TRXD collision detection time (tdet(col)(TRXD)) in star configuration.
6.9 Status register
The status register can be read out on pin ERRN by using pin EN as clock; the status bits are given in Table 10. The timing diagram is illustrated in Figure 11. The status register is accessible if:
* UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V * UVVCC flag is not set and the voltage on pin VIO is between 2.2 V and 4.75 V
After reading the status register, if no edge is detected on pin EN for longer than tdet(EN), the status bits (S4 to S12) will be cleared if the corresponding flag has been reset. Pin ERRN is LOW if the corresponding status bit is set.
Table 10. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 Status bits Description local wake-up source flag is redirected to this bit remote wake-up source flag is redirected to this bit node configuration flag is redirected to this bit status bit set means PWON flag has been set previously status bit set means bus error flag has been set previously status bit set means temperature high flag has been set previously status bit set means temperature medium flag has been set previously status bit set means TXEN_BGE clamped flag has been set previously status bit set means UVVBAT flag has been set previously status bit set means UVVCC flag has been set previously status bit set means UVVIO flag has been set previously status bit is set if Star-locked mode has been entered previously status bit is set if a TRXD collision has been detected previously LOCAL WAKEUP REMOTE WAKEUP NODE CONFIG PWON BUS ERROR TEMP HIGH TEMP MEDIUM TXEN_BGE CLAMPED UVVBAT UVVCC UVVIO STAR LOCKED TRXD COLLISION
Bit number Status bit
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normal
receive only
STBN tdet(EN) 0.7VIO
0.7VIO
EN TEN 0.7VIO 0.3VIO
td(EN-ERRN) S0 S1 S2
001aag896
ERRN
Fig 11. Timing diagram for status bits
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7. Limiting values
Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VBAT VCC VBUF VIO VINH1 VINH2 VWAKE Io(WAKE) VBGE VTXEN VTXD VERRN VRXD VRXEN VEN VSTBN VTRXD0 VTRXD1 VBP VBM Vtrt Parameter supply voltage on pin VBAT supply voltage supply voltage on pin VBUF supply voltage on pin VIO voltage on pin INH1 voltage on pin INH2 voltage on pin WAKE output current on pin WAKE voltage on pin BGE voltage on pin TXEN voltage on pin TXD voltage on pin ERRN voltage on pin RXD voltage on pin RXEN voltage on pin EN voltage on pin STBN voltage on pin TRXD0 voltage on pin TRXD1 voltage on pin BP voltage on pin BM transient voltage pin GND not connected no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit on pins BP and BM on pin VBAT on pin VBAT on pin VBAT Tstg Tvj VESD storage temperature virtual junction temperature electrostatic discharge voltage HBM on pins BP and BM to ground HBM at any other pin MM on all pins CDM on all pins
[1] [2] [3] [4]
[5] [6] [7] [8] [9] [1] [2] [3] [4]
Conditions no time limit operating range no time limit operating range no time limit operating range no time limit operating range
Min -0.3 6.5 -0.3 4.75 -0.3 4.75 -0.3 2.2 -0.3 -0.3 -0.3 -15 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -60 -60 -200 -200 6.5 -55 -40 -8.0 -4.0 -200 -1000
Max +60 60 +5.5 5.25 +5.5 5.25 +5.5 5.25 VBAT + 0.3 VBAT + 0.3 VBAT + 0.3 +5.5 +5.5 +5.5 VIO + 0.3 VIO + 0.3 VIO + 0.3 +5.5 +5.5 +5.5 +5.5 +60 +60 +200 +200 60 60 +150 +150 +8.0 +4.0 +200 +1000
Unit V V V V V V V V V V V mA V V V V V V V V V V V V V V V V C C kV kV V V
According to ISO 7637, part 3 test pulses a and b; Class C; see Figure 15; RL = 45 ; CL = 100 pF. According to ISO 7637, part 2 test pulses 1, 2, 3a and 3b; Class C; see Figure 15; RL = 45 ; CL = 100 pF. According to ISO 7637, part 2 test pulse 4; Class C; see Figure 15; RL = 45 ; CL = 100 pF. According to ISO 7637, part 2 test pulse 5b; Class C; see Figure 15; RL = 45 ; CL = 100 pF; VBAT = 24 V.
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[5]
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + P x Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). HBM: C = 100 pF; R = 1.5 k. HBM: C = 100 pF; R = 1.5 k. MM: C = 200 pF; L = 0.75 H; R = 10 . CDM: R = 1 .
[6] [7] [8] [9]
8. Thermal characteristics
Table 12. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 126 Unit K/W
9. Static characteristics
Table 13. Static characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pin VBAT IBAT supply current on pin VBAT low power modes in node configuration; no load on pins IHN1 and IHN2 Star-sleep mode Star-standby mode; no load on pins IHN1 and IHN2 normal power modes Vuvd(VBAT) Pin VCC ICC supply current low power modes Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode; Star-idle mode Normal mode; VBGE = VIO; VTXEN = 0 V; VBUF open Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus = Star-transmit mode Star-receive mode Vuvd(VCC) Pin VIO IIO supply current on pin VIO low power modes Normal and Receive-only modes; VTXD = VIO
TJA1080A_4
Parameter
Conditions
Min -
Typ -
Max 55
Unit A
2.75
-
55 150 1 4.5
A A mA V
undervoltage detection voltage on pin VBAT
-1 -
0 -
+10 15
A mA
[1]
2.75
-
35 15 62 42 4.5
mA mA mA mA V
undervoltage detection voltage on pin VCC
VBAT > 5.5 V
-1 -
+1 -
+10 1000
A A
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Table 13. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Vuvd(VIO) Vuvr(VIO) Vuvhys(VIO) Pin VBUF IBUF supply current on pin VBUF low power modes in node configuration low power modes in star configuration VBUF = 0 V; VCC = 0 V VBUF = 5.25 V Normal mode; VBGE = VIO; VTXEN = 0 V; VBUF = VCC Star-transmit mode Star-receive mode Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode; Star-idle mode VBUF(on) on-state voltage on pin VBUF VCC switch is switched on; Normal mode; VBGE = VIO; VTXEN = 0 V; VCC > maximum value of Vuvd(VCC) VCC switch is switched off; low power modes in star configuration; VCC < minimum value of Vuvd(VCC)
[1]
Parameter undervoltage detection voltage on pin VIO undervoltage recovery voltage on pin VIO undervoltage hysteresis voltage on pin VIO
Conditions
Min 1 1
Typ -
Max 2 2.2 200
Unit V V mV
VBAT > 5.5 V
25
-1
0
+10
A
-40 -1 -
-20 0 -
+1 +15 35 62 42 15
A A mA mA mA mA
VCC - 0.25 -
VCC
V
VBUF(off)
off-state voltage on pin VBUF
4.5
-
5.25
V
Pin EN VIH(EN) VIL(EN) IIH(EN) IIL(EN) HIGH-level input voltage on pin EN LOW-level input voltage on pin EN HIGH-level input current on pin EN LOW-level input current on pin EN VEN = 0.7VIO VEN = 0 V 0.7VIO -0.3 3 -1 0 5.5 0.3VIO 11 +1 V V A A
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Table 13. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pin STBN VIH(STBN) VIL(STBN) IIH(STBN) IIL(STBN) Pin TXEN VIH(TXEN) VIL(TXEN) IIH(TXEN) IIL(TXEN) IL(TXEN) Pin BGE VIH(BGE) VIL(BGE) IIH(BGE) IIL(BGE) Pin TXD VIH(TXD) VIL(TXD) IIH(TXD) IIL(TXD) HIGH-level input voltage on pin TXD LOW-level input voltage on pin TXD HIGH-level input current on pin TXD LOW-level input current on pin TXD input leakage current on pin TXD input capacitance on pin TXD normal power modes normal power modes VTXD = VIO normal power modes; VTXD = 0 V low power modes ILI(TXD) Ci(TXD) VTXD = 5.25 V; VIO = 0 V not tested; with respect to all other pins at ground; VTXD = 100 mV; f = 5 MHz
[2]
Parameter HIGH-level input voltage on pin STBN LOW-level input voltage on pin STBN HIGH-level input current on pin STBN LOW-level input current on pin STBN HIGH-level input voltage on pin TXEN LOW-level input voltage on pin TXEN HIGH-level input current on pin TXEN LOW-level input current on pin TXEN leakage current on pin TXEN HIGH-level input voltage on pin BGE LOW-level input voltage on pin BGE HIGH-level input current on pin BGE LOW-level input current on pin BGE
Conditions
Min 0.7VIO -0.3
Typ 0
Max 5.5 0.3VIO 11 +1
Unit V V A A
VSTBN = 0.7VIO VSTBN = 0 V
3 -1
0.7VIO -0.3 VTXEN = VIO VTXEN = 0.3VIO VTXEN = 5.25 V; VIO = 0 V -1 -15 -1
0 0
5.5 0.3VIO +1 -3 +1
V V A A A
0.7VIO -0.3 VBGE = 0.7VIO VBGE = 0 V 3 -1
0
5.5 0.3VIO 11 +1
V V A A
0.7VIO -0.3 70 -5 -1 -1 -
300 0 0 0 5
VIO + 0.3 0.3VIO 650 +5 +1 +1 10
V V A A A A pF
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Table 13. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pin RXD IOH(RXD) IOL(RXD) Pin ERRN IOH(ERRN) HIGH-level output current node configuration; on pin ERRN VERRN = VIO - 0.4 V; VIO = VCC star configuration; VERRN = VIO - 0.4 V; VIO = VCC IOL(ERRN) Pin RXEN IOH(RXEN) IOL(RXEN) HIGH-level output current VRXEN = VIO - 0.4 V; on pin RXEN VIO = VCC LOW-level output current on pin RXEN HIGH-level input voltage on pin TRXD0 LOW-level input voltage on pin TRXD0 LOW-level output voltage on pin TRXD0 HIGH-level input voltage on pin TRXD1 LOW-level input voltage on pin TRXD1 LOW-level output voltage on pin TRXD1 idle output voltage on pin BP VRXEN = 0.4 V -4 1 -1.5 3 -0.5 8 mA mA LOW-level output current on pin ERRN VERRN = 0.4 V -1500 -550 -100 A HIGH-level output current VRXD = VIO - 0.4 V; VIO = VCC on pin RXD LOW-level output current on pin RXD VRXD = 0.4 V -20 2 -2 20 mA mA Parameter Conditions Min Typ Max Unit
-1
0
+1
A
300
700
1500
A
Pins TRXD0 and TRXD1 VIH(TRXD0) VIL(TRXD0) VOL(TRXD0) VIH(TRXD1) VIL(TRXD1) VOL(TRXD1) Star-idle and Star-transmit modes Star-idle and Star-transmit modes Rpu = 200 Star-idle and Star-transmit modes Star-idle and Star-transmit modes Rpu = 200 0.7VBUF -0.3 -0.3 0.7VBUF -0.3 -0.3 VBUF + 0.3 V 0.3VBUF +0.8 V V
VBUF + 0.3 V 0.3VBUF +0.8 V V
Pins BP and BM Vo(idle)(BP) Normal, Receive-only, Star-idle, Star-transmit and Star-receive modes; VTXEN = VIO Standby, Go-to-sleep, Sleep, Star-standby and Star-sleep modes 0.4VBUF 0.5VBUF 0.6VBUF V
-0.1
0
+0.1
V
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FlexRay transceiver
Table 13. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Vo(idle)(BM) Parameter idle output voltage on pin BM Conditions Normal, Receive-only, Star-idle, Star-transmit and Star-receive modes; VTXEN = VIO Standby, Go-to-sleep, Sleep, Star-standby and Star-sleep modes Io(idle)BP Io(idle)BM Vo(idle)(dif) VOH(dif) VOL(dif) VIH(dif) idle output current on pin BP idle output current on pin BM differential idle output voltage differential HIGH-level output voltage differential LOW-level output voltage differential HIGH-level input voltage differential LOW-level input voltage 40 Rbus 55 VCC = VBUF = 5 V 40 Rbus 55 VCC = VBUF = 5 V normal power modes -10 V VBP +15 V -10 V VBM +15 V normal power modes -10 V VBP +15 V -10 V VBM +15 V low power modes -10 V VBP +15 V -10 V VBM +15 V Vi(dif)(H-L) differential input voltage normal power modes difference between (VBP + VBM) / 2 = 2.5 V HIGH-level and LOW-level activity detection differential input voltage (absolute value) short-circuit output current on pin BP (absolute value) short-circuit output current on pin BM (absolute value) input resistance on pin BM differential input resistance between pin BP and pin BM input leakage current on pin BP normal power modes -60 V |VBP| +60 V -60 V |VBM| +60 V Min 0.4VBUF Typ 0.5VBUF Max 0.6VBUF Unit V
-0.1
0
+0.1
V
-7.5 -7.5 -25 600 -1500 150
0 800 -800 225
+7.5 +7.5 +25 1500 -600 300
mA mA mV mV mV mV
VIL(dif)
-300
-225
-150
mV
-400
-225
-125
mV
-
-
10
%
|Vi(dif)det(act)|
150
225
300
mV
|Io(sc)(BP)|
VBP = 0 V, 60 V
10
20
35
mA
|Io(sc)(BM)|
VBM = 0 V, 60 V
10
20
35
mA
Ri(BP) Ri(BM) Ri(dif)(BP-BM)
input resistance on pin BP idle level; Rbus = idle level; Rbus = idle level; Rbus =
10 10 20
20 20 40
40 40 80
k k k
ILI(BP)
VBP = 5 V; VBAT = VCC = VIO = 0 V
-10
0
+10
A
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FlexRay transceiver
Table 13. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol ILI(BM) Parameter input leakage current on pin BM Conditions VBM = 5 V; VBAT = VCC = VIO = 0 V Rbus = 45 Rbus = 45 Rbus = 45 not tested; with respect to all other pins at ground; VBP = 100 mV; f = 5 MHz not tested; with respect to all other pins at ground; VBM = 100 mV; f = 5 MHz not tested; with respect to all other pins at ground; V(BM-BP) = 100 mV; f = 5 MHz
[2]
Min -10 0.4VBUF 0.4VBUF -25 -
Typ 0 0.5VBUF 0.5VBUF 0 8
Max +10 0.6VBUF 0.6VBUF +25 15
Unit A V V mV pF
Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Vcm(bus) Ci(BP) bus common-mode voltage difference input capacitance on pin BP input capacitance on pin BM differential input capacitance between pin BP and pin BM
Ci(BM)
[2]
-
8
15
pF
Ci(dif)(BP-BM)
[2]
-
2
5
pF
Pin INH1 VOH(INH1) IL(INH1) IOL(INH1) Pin INH2 VOH(INH2) IL(INH2) IOL(INH2) Pin WAKE Vth(det)(WAKE) IIL(WAKE) IIH(WAKE) detection threshold voltage on pin WAKE LOW-level input current on pin WAKE HIGH-level input current on pin WAKE medium warning junction temperature high disable junction temperature low power mode VWAKE = 2.4 V for t > twake(WAKE) VWAKE = 4.6 V for t > twake(WAKE) VBAT > 5.5 V VBAT > 5.5 V 2.5 3 -11 4.5 11 -3 V A A HIGH-level output voltage IINH2 = -0.2 mA on pin INH2 leakage current on pin INH2 LOW-level output current on pin INH2 Sleep mode VINH2 = 0 V VBAT - 0.8 -5 -15 0 VBAT +5 V A mA HIGH-level output voltage IINH1 = -0.2 mA on pin INH1 leakage current on pin INH1 LOW-level output current on pin INH1 Sleep mode VINH1 = 0 V VBAT - 0.8 -5 -15 0 VBAT +5 V A mA
Temperature protection Tj(warn)(medium) Tj(dis)(high) 155 180 165 190 175 200 C C
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Table 13. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Power-on reset Vth(det)POR Vth(rec)POR Vhys(POR) power-on reset detection threshold voltage power-on reset recovery threshold voltage power-on reset hysteresis voltage 3.0 3.1 100 3.4 3.5 200 V V mV Parameter Conditions Min Typ Max Unit
[1] [2]
Current flows from VCC to VBUF. This means that the maximum sum current ICC + IBUF is 35 mA. These values are based on measurements taken on several samples (less than 10 pieces). These measurements have taken place in the laboratory and have been done at Tamb = 25 C and Tamb = 125 C. No characterization has been done for these parameters. No industrial test will be performed on production products.
10. Dynamic characteristics
Table 14. Dynamic characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol td(TXD-bus) Parameter delay time from TXD to bus Conditions Normal or Star-transmit mode DATA_0 DATA_1 td(TXD-bus) td(TRXD-bus) delay time difference from TXD to bus delay time from TRXD to bus Normal or Star-transmit mode; between DATA_0 and DATA_1 Star-transmit mode DATA_0 DATA_1 td(TRXD-bus) td(bus-RXD) delay time difference from TRXD Star-transmit mode; between to bus DATA_0 and DATA_1 delay time from bus to RXD Normal or Star-transmit mode; CRXD = 15 pF; see Figure 13 DATA_0 DATA_1 td(bus-RXD) delay time difference from bus to Normal or Star-transmit mode; RXD CRXD = 15 pF; between DATA_0 and DATA_1; see Figure 13 delay time from bus to TRXD Star-receive mode; see Figure 13 DATA_0 DATA_1 50 50 ns ns 50 50 5 ns ns ns
[2][3] [1] [1]
Min
Typ
Max
Unit
Pins BP and BM 50 50 4 ns ns ns
[2]
-
-
50 50 5
ns ns ns
td(bus-TRXD)
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Table 14. Dynamic characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol td(bus-TRXD) Parameter Conditions
[3]
Min -
Typ -
Max 5
Unit ns
delay time difference from bus to Star-receive mode; between TRXD DATA_0 and DATA_1; see Figure 13 delay time from TXEN to bus idle Normal mode delay time from TXEN to bus active delay time from BGE to bus idle delay time from BGE to bus active Normal mode Normal mode Normal mode
td(TXEN-busidle) td(TXEN-busact) td(BGE-busidle) td(BGE-busact) td(bus)(idle-act) td(bus)(act-idle) tr(dif)(bus) tf(dif)(bus)
5 5
12 12
100 75 100 75 30 30 25 25
ns ns ns ns ns ns ns ns
bus delay time from idle to active Normal mode bus delay time from active to idle Normal mode bus differential rise time bus differential fall time 10 % to 90 % RL = 45 ; CL = 100 pF 90 % to 10 % RL = 45 CL = 100 pF Standby, Sleep, Star-standby or Star-sleep modes 10 V VBP +15 V 10 V VBM +15 V
WAKE symbol detection tdet(wake)DATA_0 tdet(wake)idle tdet(wake)tot Undervoltage tdet(uv)(VCC) trec(uv)(VCC) tdet(uv)(VIO) tto(uv)(VCC) undervoltage detection time on pin VCC undervoltage recovery time on pin VCC undervoltage detection time on pin VIO undervoltage time-out time on pin VCC for entering Standby mode undervoltage detection time on pin VBAT activity detection time on pin TXEN activity detection time on pin TRXD activity detection time on bus pins idle detection time on pin TXEN idle detection time on pin TRXD idle detection time on bus pins star configuration star configuration Vdif: 0 mV 400 mV star configuration star configuration Vdif: 400 mV 0 mV star configuration; wake flag is set 100 1 100 432 670 5.2 670 900 ms ms ms s DATA_0 wake-up detection time idle wake-up detection time total wake-up detection time 1 1 50 4 4 115 s s s
tdet(uv)(VBAT)
-
-
1
ms
Activity detection tdet(act)(TXEN) tdet(act)(TRXD) tdet(act)(bus) tdet(idle)(TXEN) tdet(idle)(TRXD) tdet(idle)(bus) Star modes 100 100 100 100 50 100 200 200 250 200 100 250 ns ns ns ns ns ns
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FlexRay transceiver
Table 14. Dynamic characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 ; RTRXD = 200 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol tto(idle-sleep) tto(tx-locked) tto(rx-locked) tto(locked-sleep) tto(locked-idle) Node modes td(STBN-RXD) td(STBN-INH2) th(gotosleep) Status register tdet(EN) TEN td(EN-ERRN) WAKE twake(WAKE) wake-up time on pin WAKE low power mode; falling edge on pin WAKE; 6.5 V VBAT 27 V low power mode; falling edge on pin WAKE; 27 V < VBAT 60 V Miscellaneous tdetCL(TXEN_BGE) TXEN_BGE clamp detection time tdet(col)(TRXD)
[1] [2] [3]
Parameter idle to sleep time-out time transmit to locked time-out time receive to locked time-out time locked to sleep time-out time locked to idle time-out time STBN to RXD delay time STBN to INH2 delay time go-to-sleep hold time detection time on pin EN time period on pin EN delay time from EN to ERRN
Conditions
Min 640 2600 2600 64 1.4
Typ 35 25 75
Max 2660 10400 10400 333 5.1 2 10 50 80 20 2 100 175
Unit ms s s ms s s s s s s s s s
STBN HIGH to RXD HIGH; wake flag set STBN LOW to INH2 floating; Normal mode
20
for mode control for reading status bits for reading status bits
20 4 5 25
2600 TRXD0 and TRXD1 20
-
10400 -
s ns
TRXD collision detection time
Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 ns 1ns. Rise and fall time (10 % to 90 %) of tr(TRXD) and tf(TRXD) = 5 ns 1ns. The worst case asymmetry from one branch to another is the sum of the delay difference from TRXD0 and TRXD1 to DATA_0 and DATA_1 plus the delay difference from DATA_0 and DATA_1 to TRXD0 and TRXD1.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 04 -- 19 February 2009
(c) NXP B.V. 2009. All rights reserved. TJA1080A_4
NXP Semiconductors
td(TXD-bus) td(TXD-bus) 0.7VIO TXD 0.3VIO td(TXEN-busidle)
td(TXEN-busact) td(BGE-busidle)
td(BGE-busact)
0.7VIO TXEN 0.3VIO
0.7VIO BGE 0.3VIO
BP and BM
+300 mV 0V -300 mV
90 % -150 mV -300 mV -150 mV -300 mV 10 %
0.7VIO RXEN 0.3VIO
0.7VIO RXD 0.3VIO td(bus-RXD) td(bus-RXD) tdet(idle)(bus) tdet(act)(bus) tdet(idle)(bus) tdet(act)(bus) tr(dif)(bus) tf(dif)(bus)
001aae445
Fig 12. Detailed timing diagram in node configuration
TJA1080ATS/2
FlexRay transceiver
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NXP Semiconductors
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Vdif (mV) 400 300
22.5 ns
22.5 ns
37.5 ns -300 -400 60 ns RXD td(bus-RXD) td(bus-RXD)
Vdif (mV) 400 300
22.5 ns
22.5 ns
37.5 ns -300 -400 60 ns RXD td(bus-RXD) td(bus-RXD)
015aaa044
Vdif is the receiver test signal.
Fig 13. Receiver test signal
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11. Test information
+12 V +5 V
100 nF 10 F 22 F
4 VIO
19 VCC
14 VBAT
20 VBUF BP 18
RL CL
TJA1080ATS/2
BM
17
RXD
7
15 pF
015aaa053
Fig 14. Test circuit for dynamic characteristics
ISO 7637
G
12 V or 42 V
+5 V
100 nF 10 F 10 F
4 VIO
19 VCC
14 VBAT
20 VBUF BP 18
RL 1 nF ISO 7637 CL
TJA1080ATS/2
BM 17
G
1 nF
015aaa054
The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 4 and 5. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz
Fig 15. Test circuit for automotive transients
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Product data sheet
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NXP Semiconductors
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FlexRay transceiver
12. Package outline
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 10 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 16. Package outline SOT339-1 (SSOP20)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 15 and 16
Table 15. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 16. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17.
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FlexRay transceiver
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Appendix
14.1 Differences between TJA1080 and TJA1080ATS/2
14.1.1 Start-up
Table 17. TJA1080 At power-up VBAT should be supplied first. When VBAT reaches 6.5 V, VCC and VIO may be switched on with a delay of at least 60 s with respect to VBAT. Start-up differences between TJA1080 and TJA1080ATS/2 TJA1080ATS/2 The TJA1080ATS/2 initialization is independent of the way the voltage supplies VBAT, VCC and VIO ramp up. A dedicated power-up sequence is not necessary.
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FlexRay transceiver
14.1.2 Bus error detection
Table 18. TJA1080 The TJA1080 expects that a data frame begins with a bit value other than the last bit of the previous data frame. This is the case for a valid data frame which begins with the DATA_0 period of the Transmission Start Sequence (TSS) and ends with the DATA_1 bit of the Frame End Sequence (FES). Any violation of this frame format will be detected by the TJA1080. Consequently, when transmitting a wake-up pattern, a bus error will be signalled. This error indication should be ignored and the status register should be cleared by reading the vector. Bus error detection differences between TJA1080 and TJA1080ATS/2 TJA1080ATS/2 The transmission of any valid communication element, including a wake-up pattern, does not lead to bus error indication.
14.1.3 Wake-up signalling via RXD pin
Table 19. TJA1080 Wake-up signalling via RXD differences between TJA1080 and TJA1080ATS/2 TJA1080ATS/2
In case of an undervoltage condition at VCC, pin In case of an undervoltage condition at VCC, pin RXD might go to LOW level. RXD can be used for correct wake-up signalling. For a correct wake-up recognition during a VCC undervoltage condition, pin RXEN can be used.
14.1.4 Asymmetric delay and minimum bit time
Table 20. TJA1080 The TJA1080 guarantees minimum bit times of 80 ns for a receiver test signal of 600 mV (see Figure 13) and asymmetric delay time of 5 ns (see Table 14). Minimum bit time differences between TJA1080 and TJA1080ATS/2 TJA1080ATS/2 The TJA1080ATS/2 guarantees minimum bit times of 60 ns for a receiver test signal of 400 mV (see Figure 13) and asymmetric delay time of less than 5 ns (see Table 14).
14.1.5 Transmitter symmetry
The transmitter symmetry has been improved with respect to the TJA1080. With this improvement, the TJA1080ATS/2 features less EME than the TJA1080.
14.1.6 Impact of input signals on pin EN
Table 21. TJA1080 Input signals on pin EN: differences between TJA1080 and TJA1080ATS/2 TJA1080ATS/2
Certain pulses on pin EN may lead to a hang-up This issue has been resolved in the of the digital input of pin EN. TJA1080ATS/2
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15. Abbreviations
Table 22. BSS CAN CDM EMC EME EMI ESD FES HBM MM PWON TSS Abbreviations Description Byte Start Sequence Controller Area Network Charged Device Model ElectroMagnetic Compatibility ElectroMagnetic Emission ElectroMagnetic Immunity ElectroStatic Discharge Frame End Sequence Human Body Model Machine Model Power-on Transmission Start Sequence Abbreviation
16. References
[1] [2] [3] [4] EPL -- FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. A, FlexRay Consortium, Dec. 2005 PS54 -- Product specification: TJA1054; Fault-tolerant CAN transceiver, www.nxp.com PS41 -- Product specification: TJA1041; High speed CAN transceiver, www.nxp.com DS80 -- Product data sheet: TJA1080; FlexRay transceiver, www.nxp.com
17. Revision history
Table 23. Revision history Release date 20090219 Data sheet status Preliminary data sheet Change notice Supersedes TJA1080A_3 Document ID TJA1080A_4 Modifications:
* * *
Product name changed to TJA1080ATS/2 Table 13: table note section revised Table 14: table note section revised Preliminary data sheet Preliminary data sheet Objective data sheet TJA1080A_2 TJA1080A_1 -
TJA1080A_3 TJA1080A_2 TJA1080A_1
20090115 20080826 20071029
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18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications only -- This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of
18.4 Licenses
Purchase of NXP ICs with FlexRay functionality FlexRay license required. This product has been developed within the framework of the "FlexRay" consortium. FlexRay consortium members are willing to grant licenses under their essential FlexRay intellectual property rights to end users of FlexRay-enabled products upon request of an end user. The sale by NXP Semiconductors of a FlexRay-enabled product will not be construed as the granting of such a license. Each end user will have to apply to the FlexRay consortium administration to obtain such a license or to apply for membership. The FlexRay consortium can be contacted at request@flexray.com.
18.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
TJA1080A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 February 2009
46 of 49
NXP Semiconductors
TJA1080ATS/2
FlexRay transceiver
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1080A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 February 2009
47 of 49
NXP Semiconductors
TJA1080ATS/2
FlexRay transceiver
20. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Low power management . . . . . . . . . . . . . . . . . 2 2.3 Diagnosis (detection and signalling) . . . . . . . . . 2 2.4 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Operating configurations. . . . . . . . . . . . . . . . . . 6 6.1.1 Node configuration . . . . . . . . . . . . . . . . . . . . . . 6 6.1.2 Star configuration . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.3 Bus activity and idle detection . . . . . . . . . . . . . 7 6.2 Operating modes in node configuration . . . . . . 7 6.2.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2.2 Receive-only mode . . . . . . . . . . . . . . . . . . . . . 14 6.2.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2.4 Go-to-sleep mode . . . . . . . . . . . . . . . . . . . . . . 14 6.2.5 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Operating modes in star configuration . . . . . . 15 6.3.1 Star-idle mode . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.2 Star-transmit mode . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 Star-receive mode . . . . . . . . . . . . . . . . . . . . . 18 6.3.4 Star-standby mode . . . . . . . . . . . . . . . . . . . . . 18 6.3.5 Star-sleep mode . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.6 Star-locked mode . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4.1 Node configuration . . . . . . . . . . . . . . . . . . . . . 19 6.4.2 Star configuration . . . . . . . . . . . . . . . . . . . . . . 19 6.5 Wake-up mechanism . . . . . . . . . . . . . . . . . . . 20 6.5.1 Node configuration . . . . . . . . . . . . . . . . . . . . . 20 6.5.2 Star configuration . . . . . . . . . . . . . . . . . . . . . . 20 6.5.3 Remote wake-up. . . . . . . . . . . . . . . . . . . . . . . 20 6.5.3.1 Bus wake-up via wake-up pattern. . . . . . . . . . 20 6.5.3.2 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5.4 Local wake-up via pin WAKE . . . . . . . . . . . . . 21 6.6 Fail silent behavior . . . . . . . . . . . . . . . . . . . . . 22 6.6.1 VBAT undervoltage. . . . . . . . . . . . . . . . . . . . . . 22 6.6.2 VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 22 1 2 2.1 6.6.3 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.7.8 6.7.9 6.7.10 6.7.11 6.7.12 6.7.13 6.8 6.9 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 14.1 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.1.6 15 16 17 18 18.1 18.2 18.3 18.4 18.5 VIO undervoltage . . . . . . . . . . . . . . . . . . . . . . Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local wake-up source flag . . . . . . . . . . . . . . . Remote wake-up source flag . . . . . . . . . . . . . Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on flag . . . . . . . . . . . . . . . . . . . . . . . . . Node configuration flag . . . . . . . . . . . . . . . . . Temperature medium flag . . . . . . . . . . . . . . . Temperature high flag . . . . . . . . . . . . . . . . . . TXEN_BGE clamped flag. . . . . . . . . . . . . . . . Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . . UVVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . . UVVIO flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . Error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRXD collision . . . . . . . . . . . . . . . . . . . . . . . . Status register . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differences between TJA1080 and TJA1080ATS/2 . . . . . . . . . . . . . . . . . . . . . . . . Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus error detection. . . . . . . . . . . . . . . . . . . . . Wake-up signalling via RXD pin . . . . . . . . . . . Asymmetric delay and minimum bit time . . . . Transmitter symmetry. . . . . . . . . . . . . . . . . . . Impact of input signals on pin EN . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 23 23 23 23 23 24 24 24 24 24 24 24 25 25 27 28 28 34 39 40 41 41 41 41 42 43 43 43 44 44 44 44 44 45 45 45 46 46 46 46 46 46
continued >>
TJA1080A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 February 2009
48 of 49
NXP Semiconductors
TJA1080ATS/2
FlexRay transceiver
19 20
Contact information. . . . . . . . . . . . . . . . . . . . . 47 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 February 2009 Document identifier: TJA1080A_4

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